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K7N403601A K7N401801A
Document Title
128Kx36 & 256Kx18 Pipelined NtRAMTM
128Kx36 & 256Kx18-Bit Pipelined NtRAM TM
Revision History
Rev. No. 0.0 0.1 History 1. Initial document. 1. Changed DC condition at Icc and ISB. Icc ; from 350mA to 400mA at -16, from 340mA to 390mA at -15, from 310mA to 360mA at -13, ISB ; from 130mA to 140mA at -16, from 120mA to 130mA at -15, from 120mA to 130mA at -13, 1.0 1. Final spec release 2. Changed input & output capacitance. CIN ; from 6pF to 5pF, COUT ; from 8pF to 7pF, May. 15. 2000 Final Draft Date Jan. 20. 2000 April. 03. 2000 Remark Preliminary Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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May 2000 Rev 1.0
K7N403601A K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
128Kx36 & 256Kx18-Bit Pipelined NtRAMTM
FEATURES
* VDD=3.3V+0.165V/-0.165V Power Supply. * VDDQ Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. * Byte Writable Function. * Enable clock and suspend operation. * Single READ/WRITE control pin. * Self-Timed Write Cycle. * Three Chip Enable for simple depth expansion with no datacontention. * interleaved burst or a linear burst mode. * Asynchronous output enable control. * Power Down mode. * TTL-Level Three-State Outputs. * 100-TQFP-1420A Package.
GENERAL DESCRIPTION
The K7N403601A and K7N401801A are 4,718,592 bits Synchronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incomming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge trigered output register and then released to the output bufferes at the next rising edge of clock. The K7N403601A and K7N401801A are implemented with SAMSUNGs high performance CMOS technology and is available in 100pin TQFP packages. Multiple power and ground pins minimize ground bounce.
FAST ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE -16 6.0 3.5 3.5 -15 6.7 3.8 3.8 -13 7.5 4.2 4.2 Unit ns ns ns
LOGIC BLOCK DIAGRAM
LBO A [0:16]or A [0:17] ADDRESS REGISTER A2~A16 or A2~A17 A0~A1
BURST ADDRESS COUNTER
A0~A1 128Kx36 , 256Kx18 MEMORY ARRAY
CLK CKE
K
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
CONTROL LOGIC
K
DATA-IN REGISTER DATA-IN REGISTER
K CS1 CS2 CS2 ADV WE BWx (x=a,b,c,d or a,b) OE ZZ DQa0 ~ DQd7 or DQa0 ~ DQb8 DQPa ~ DQPd 36 or 18
CONTROL REGISTER
CONTROL LOGIC
K
OUTPUT REGISTER BUFFER
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung,
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May 2000 Rev 1.0
K7N403601A K7N401801A
PIN CONFIGURATION(TOP VIEW)
BWd BWb
128Kx36 & 256Kx18 Pipelined NtRAMTM
BWa
BWc
CKE
ADV
N.C.
N.C. 83
CLK
CS1
CS2
CS2
VDD
VSS
WE
OE
A6
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
VDD
A5
A4
A3
A2
A1
A0
A10
A11
A12
A13
A14
A15
PIN NAME
SYMBOL A0 - A16 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37 44,45,46,47,48,49 50,81,82,99,100 85 88 89 87 98 97 92 93,94,95,96 86 64 31 SYMBOL VDD VSS N.C. DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~Pd VDDQ VSSQ PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs TQFP PIN NO. 14,15,16,41,65,66,91 17,40,67,90 38,39,42,43,83,84 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76
ADV WE CLK CKE CS1 CS2 CS2 BWx(x=a,b,c,d) OE ZZ LBO
Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control
LBO
VSS
Output Power Supply (2.5V or 3.3V) Output Ground
Notes : 1. The pin 83 is reserved for address bit for the 8Mb NtRAM. 2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
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A16
50
DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 VDD VDD VDD VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 DQPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
K7N403601A(128Kx36)
DQPb DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS VDD VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa
May 2000 Rev 1.0
K7N403601A K7N401801A
PIN CONFIGURATION(TOP VIEW)
BWb
128Kx36 & 256Kx18 Pipelined NtRAMTM
BWa
CKE
ADV
CS2 N.C.
N.C.
N.C.
N.C. 83
CLK
CS1
CS2
VDD
VSS
WE
OE
A6
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
VDD
A5
A4
A3
A2
A1
A0
A11
A12
A13
A14
A15
A16
PIN NAME
SYMBOL A0 - A17 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37, 44,45,46,47,48,49 50,80,81,82,99,100 85 88 89 87 98 97 92 93,94 86 64 31 SYMBOL VDD VSS N.C. PIN NAME TQFP PIN NO. Power Supply(+3.3V) 14,15,16,41,65,66,91 Ground 17,40,67,90 No Connect 1,2,3,6,7,25,28,29,30, 38,39,42,43,51,52,53, 56,57,75,78,79,83,84 95,96 Data Inputs/Outputs 58,59,62,63,68,69,72,73,74 8,9,12,13,18,19,22,23,24
ADV WE CLK CKE CS1 CS2 CS2 BWx(x=a,b) OE ZZ LBO
Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control
LBO
VSS
DQa0~a8 DQb0~b8
VDDQ VSSQ
Output Power Supply 4,11,20,27,54,61,70,77 (2.5V or 3.3V) Output Ground 5,10,21,26,55,60,71,76
Notes : 1. The pin 83 is reserved for address bit for the 8Mb NtRAM. 2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
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A17
50
N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. DQb8 DQb7 VSSQ VDDQ DQb6 DQb5 VDD VDD VDD VSS DQb4 DQb3 VDDQ VSSQ DQb2 DQb1 DQb0 N.C. VSSQ VDDQ N.C. N.C. N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
K7N401801A(256Kx18)
A10 N.C. N.C. VDDQ VSSQ N.C. DQa0 DQa1 DQa2 VSSQ VDDQ DQa3 DQa4 VSS VDD VDD ZZ DQa5 DQa6 VDDQ VSSQ DQa7 DQa8 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C.
May 2000 Rev 1.0
K7N403601A K7N401801A
FUNCTION DESCRIPTION
128Kx36 & 256Kx18 Pipelined NtRAMTM
The K7N403601A and K7N401801A are NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NtRAMTM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2) are active . Output Enable(OE) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must be driven low for the device to drive out the requested data. Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipelined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up time.
BURST SEQUENCE TABLE
LBO PIN HIGH First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 0 1 1 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3
(Interleaved Burst, LBO=High)
Case 4 A0 0 1 0 1 A1 1 1 0 0 A0 1 0 1 0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
BQ TABLE
LBO PIN LOW First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 1 1 0 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3
(Linear Burst, LBO=Low)
Case 4 A0 0 1 0 1 A1 1 0 0 1 A0 1 0 1 0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
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May 2000 Rev 1.0
K7N403601A K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
STATE DIAGRAM FOR NtRAMTM
WRITE READ
READ
BEGIN READ
RE AD DS
ST
BEGIN WRITE
I WR TE DS
BU R W RI
WRITE
D
DESELECT
DS
RE A
BUR
ST
TE
BURST
DS
DS
BURST
BURST READ
W
R
IT E
R EA D
BURST WRITE
BURST
COMMAND DS READ WRITE BURST DESELECT BEGIN READ BEGIN WRITE BEGIN READ BEGIN WRITE CONTINUE DESELECT
ACTION
Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK)
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May 2000 Rev 1.0
K7N403601A K7N401801A
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1 H X X X L X L X L X L X X CS2 X L X X H X H X H X H X X CS2 X X H X L X L X L X L X X ADV L L L H L H L H L H L H X WE X X X X H X H X L X L X X BWx X X X X X X X X L L H H X OE X X X X L L H H X X X X X CKE L L L L L L L L L L L L H
128Kx36 & 256Kx18 Pipelined NtRAMTM
CLK
ADDRESS ACCESSED N/A N/A N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address
OPERATION Not Selected Not Selected Not Selected Not Selected Continue Begin Burst Read Cycle Continue Burst Read Cycle NOP/Dummy Read Dummy Read Begin Burst Write Cycle Continue Burst Write Cycle NOP/Write Abort Write Abort Ignore Clock
Notes : 1. X means "Dont Care".
2. The rising edge of clock is symbolized by ().
3. A continue deselect cycle can only be enterd if a deselect cycle is executed first. 4. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE(x36)
WE H L L L L L L BWa X L H H H L H BWb X H L H H L H BWc X H H L H L H BWd X H H H L L H OPERATION READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP
Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
WRITE TRUTH TABLE(x18)
WE H L L L L
Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
BWa X L H L H
BWb X H L L H
OPERATION READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ABORT/NOP
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May 2000 Rev 1.0
K7N403601A K7N401801A
ASYNCHRONOUS TRUTH TABLE
OPERATION Sleep Mode Read Write Deselected ZZ H L L L L OE X L H X X
128Kx36 & 256Kx18 Pipelined NtRAMTM
Notes 1. X means "Dont Care". 2. Sleep Mode means power Sleep Mode of which stand-by current does not depend on cycle time. 3. Deselected means power Sleep Mode of which stand-by current depends on cycle time.
I/O STATUS High-Z DQ High-Z Din, High-Z High-Z
ABSOLUTE MAXIMUM RATINGS*
PARAMETER Voltage on VDD Supply Relative to VSS Voltage on Any Other Pin Relative to VSS Power Dissipation Storage Temperature Operating Temperature Storage Temperature Range Under Bias SYMBOL VDD VIN PD TSTG TOPR TBIAS RATING -0.3 to 4.6 -0.3 to VDD+0.5 1.4 -65 to 150 0 to 70 -10 to 85 UNIT V V W C C C
*Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O(0C TA 70C)
PARAMETER Supply Voltage Ground SYMBOL VDD VDDQ VSS MIN 3.135 3.135 0 Typ. 3.3 3.3 0 MAX 3.465 3.465 0 UNIT V V V
OPERATING CONDITIONS at 2.5V I/O(0C TA 70C)
PARAMETER Supply Voltage Ground SYMBOL VDD VDDQ VSS MIN 3.135 2.375 0 Typ. 3.3 2.5 0 MAX 3.465 2.9 0 UNIT V V V
CAPACITANCE*(TA=25C, f=1MHz)
PARAMETER Input Capacitance Output Capacitance
*Note : Sampled not 100% tested.
SYMBOL CIN COUT
TEST CONDITION VIN=0V VOUT=0V
MIN -
MAX 5 7
UNIT pF pF
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May 2000 Rev 1.0
K7N403601A K7N401801A
PARAMETER Input Leakage Current(except ZZ) Output Leakage Current Operating Current SYMBOL IIL IOL ICC
128Kx36 & 256Kx18 Pipelined NtRAMTM
MIN -2 -2 -16 -15 -13 -16 -15 -13 2.4 2.0 -0.3* 2.0 -0.3* 1.7 MAX +2 +2 400 390 360 140 130 130 100 50 0.4 0.4 0.8 VDD+0.5** 0.7 VDD+0.5** mA mA V V V V V V V V 3 3 mA mA 1,2
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0C to +70C)
TEST CONDITIONS VDD=Max ; VIN=VSS to VDD Output Disabled, VDD=Max IOUT=0mA Cycle Time tCYC Min Device deselected, IOUT=0mA, ZZVIL, f=Max, All Inputs0.2V or VDD-0.2V UNIT A A NOTES
ISB Standby Current ISB1 ISB2 Output Low Voltage(3.3V I/O) Output High Voltage(3.3V I/O) Output Low Voltage(2.5V I/O) Output High Voltage(2.5V I/O) Input Low Voltage(3.3V I/O) Input High Voltage(3.3V I/O) Input Low Voltage(2.5V I/O) Input High Voltage(2.5V I/O) VOL VOH VOL VOH VIL VIH VIL VIH
Device deselected, IOUT=0mA, ZZ0.2V, f=0, All Inputs=fixed (VDD-0.2V or 0.2V) Device deselected, IOUT=0mA, ZZVDD-0.2V, f=Max, All InputsVIL or VIH IOL=8.0mA IOH=-4.0mA IOL=1.0mA IOH=-1.0mA
Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. Data states are all zero. 3. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
VIH
VSS
VSS-1.0V 20% tCYC(MIN)
TEST CONDITIONS
(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70C)
PARAMETER Input Pulse Level(for 3.3V I/O) Input Pulse Level(for 2.5V I/O) Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O) Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O) Input and Output Timing Reference Levels for 3.3V I/O Input and Output Timing Reference Levels for 2.5V I/O Output Load
VALUE 0 to 3.0V 0 to 2.5V 1.0V/ns 1.0V/ns 1.5V VDDQ/2 See Fig. 1
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May 2000 Rev 1.0
K7N403601A K7N401801A
Output Load(A)
128Kx36 & 256Kx18 Pipelined NtRAMTM
Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) RL=50 +3.3V for 3.3V I/O /+2.5V for 2.5V I/O VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O Dout 353 / 1538 319 / 1667
Dout Zo=50
30pF*
5pF*
* Including Scope and Jig Capacitance Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0C to +70C)
PARAMETER Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width Clock Low Pulse Width Address Setup to Clock High CKE Setup to Clock High Data Setup to Clock High Write Setup to Clock High (WE, BWX) Address Advance Setup to Clock High Chip Select Setup to Clock High Address Hold from Clock High CKE Hold from Clock High Data Hold from Clock High Write Hold from Clock High (WE, BWEX) Address Advance Hold from Clock High Chip Select Hold from Clock High ZZ High to Power Down ZZ Low to Power Up Symbol tCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tCH tCL tAS tCES tDS tWS tADVS tCSS tAH tCEH tDH tWH tADVH tCSH tPDS tPUS -16 Min 6.0 1.5 1.5 0 2.5 2.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 2 2 Max 3.5 3.5 3.5 3.5 Min 6.7 1.5 1.5 0 2.5 2.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 2 2 -15 Max 3.8 3.8 3.5 3.5 Min 7.5 1.5 1.5 0 3.0 3.0 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 2 2 -13 Max 4.2 4.2 3.8 3.8 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cycle cycle
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled. 3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low, Both cases must meet setup and hold times. 4. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC. The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions (0C,3.465V) than tHZC, which is a Max. parameter(worst case at 70C,3.135V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
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May 2000 Rev 1.0
K7N403601A K7N401801A
SLEEP MODE
128Kx36 & 256Kx18 Pipelined NtRAMTM
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SLEEP MODE is dictated by the length of time the ZZ is in a High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION Current during SLEEP MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to SLEEP current ZZ inactive to exit SLEEP current CONDITIONS ZZ VIH SYMBOL ISB2 tPDS tPUS tZZI tRZZI 0 2 2 2 MIN MAX 10 UNITS mA cycle cycle cycle
SLEEP MODE WAVEFORM
K
tPDS ZZ setup cycle tPUS ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2 tRZZI
All inputs (except ZZ)
Deselect or Read Only
Deselect or Read Only Normal operation cycle
Outputs (Q)
High-Z
DONT CARE
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May 2000 Rev 1.0
TIMING WAVEFORM OF READ CYCLE
tCH tCL
Clock
tCYC tCES tCEH
K7N403601A K7N401801A
CKE
tAS tAH A2 A3
Address
A1
tWS
tWH
WRITE
128Kx36 & 256Kx18 Pipelined NtRAMTM
- 12 tCSH tADVH tOE tHZOE Q1-1 tLZOE tCD tOH Q2-1 Q2-2 Q2-3
tCSS
CS
tADVS
ADV
OE
tHZC Q2-4 Q3-1 Q3-2 Q3-3 Q3-4
Data Out
May 2000 Rev 1.0
NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
Dont Care Undefined
TIMING WAVEFORM OF WRTE CYCLE
tCH tCL
Clock
tCYC
K7N403601A K7N401801A
tCES tCEH
CKE
Address
A2 A3
A1
WRITE
128Kx36 & 256Kx18 Pipelined NtRAMTM
- 13 D1-1 tHZOE Q0-4 D2-1 D2-2 D2-3
CS
ADV
OE
tDS D2-4 D3-1 D3-2 tDH D3-3 D3-4
Data In
Data Out
Q0-3
Dont Care Undefined
May 2000 Rev 1.0
NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
TIMING WAVEFORM OF SINGLE READ/WRITE
tCH tCL
Clock
tCYC
K7N403601A K7N401801A
tCES tCEH
CKE
Address
A2 A3 A4 A5 A6 A7
A1
A8
A9
WRITE
128Kx36 & 256Kx18 Pipelined NtRAMTM
- 14 tOE tLZOE Q1 tDS D2 tDH Q3 Q4
CS
ADV
OE
Data Out
Q6
Q7
Data In
D5
May 2000 Rev 1.0
NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
Dont Care Undefined
TIMING WAVEFORM OF CKE OPERATION
tCH tCL
Clock
tCYC
K7N403601A K7N401801A
tCES tCEH
CKE
Address
A2 A3 A4
A1
A5
A6
WRITE
128Kx36 & 256Kx18 Pipelined NtRAMTM
- 15 tCD tLZC tHZC Q1 tDS
CS
ADV
OE
Data Out
Q3 tDH D2
Q4
Data In
Dont Care Undefined
May 2000 Rev 1.0
NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
TIMING WAVEFORM OF CS OPERATION
tCH tCL
Clock
tCYC
K7N403601A K7N401801A
tCES
tCEH
CKE
Address
A2 A3 A4 A5
A1
WRITE
128Kx36 & 256Kx18 Pipelined NtRAMTM
- 16 tOE tLZOE Q1 Q2 tDS tDH D3 tHZC tCD tLZC
CS
ADV
OE
Data Out
Q4
Data In
D5
Dont Care Undefined
May 2000 Rev 1.0
NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
K7N403601A K7N401801A
PACKAGE DIMENSIONS
100-TQFP-1420A
22.00 0.30 20.00 0.20
128Kx36 & 256Kx18 Pipelined NtRAMTM
Units ; millimeters/Inches
0~8
0.10 0.127 + 0.05 -
16.00 0.30 14.00 0.20 0.10 MAX
(0.83) 0.50 #1 0.65 0.30 0.10 0.10 MAX (0.58)
0.10
1.40 0.10 1.60 MAX 0.50
0.10
0.05 MIN
- 17 -
May 2000 Rev 1.0

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